NUMA support ( Non-Uniform Memory Access, memory design for multiprocessors) allows virtual machines to efficiently access large amounts of memory. NUMA支持(非一致性内存访问,针对多处理器的内存设计)允许虚拟机有效地访问大量内存。
Standard CMOS Process-based OTP Memory Design and Research 基于标准CMOS工艺的OTP存储器的设计与研究
Before computers it would have taken someone with an autistic-type memory to design great cathedrals, while scientists such as Isaac Newton and Albert Einstein show every sign of having been autistic. 在有计算机以前,设计一个大教堂就需要一个有类似于孤独症患者那样的记忆力的设计师。像牛顿和爱因斯坦这样的科学家也表现得很像孤独症患者。
Memory Design in Embryonic Bio-inspired Circuit with Self-Repairing Properties 胚胎型仿生电路中具有自修复性能的存储器设计
Standard logic cells, memory design and IO Layout design. 标准逻辑单元,存储电路设计及输入输出单元版图设计。
In the third part of this thesis, a memory BISR design automation framework is proposed to plan and generate BISR circuits for RAMs in an SOC. 论文第三部分,提出一记忆体BISR之设计自动化基础框架(BISRdesignautomationframework),可针对系统晶片中之多记忆体模组,规划与自动产生BISR电路。
No necessary to adjust the heels' shape.3.The side-pressing mechanism adopts automatic balance memory forming design. 压边机构采用自动平衡记忆成形设计,使鞋底与鞋面强力贴合,不留空隙。
The Techniques of Image Memory Design 图形存储器的设计技术
N-Channel MOS memories-new possibilities for microprocessor memory design MCM7001型N-沟道MOS随机存储器&为微型信息处理机存储器设计提供新的可能性
Fault-Tolerant Memory System Design in SoC Real-time Digital Signal Processing System 基于SoC的实时信号处理系统中存储系统的容错设计
Memory Controller Design of System-on-a-Chip 系统芯片中的存储器接口电路设计
With memories accounting for the large share of power consumption in the microprocessor, especially in SoC ( System on Chip), low-power memory design technologies have significant meaning to the development of IC design. 在微处理器特别是SoC(系统集成芯片)中,由于存储器占据了芯片功耗的很大部分,因此低功耗存储器的设计技术对集成电路发展具有重要意义。
There are two methods to be used to design the single clock generic FIFO memory. In the single clock FIFO memory design, the combinatorial and registered status outputs are designed as two output ways so that users choose one way to output status considering design requirements. 在单时钟通用FIFO设计中讨论了两种设计方法,每一种设计方法均具有两种输出方式:组合逻辑输出和寄存器输出,以备用户根据具体情况选择不同的输出方式;
Memory controller design and IP interconnection are the common issues in System-on-a-Chip ( SoC) design. 存储器控制电路的设计和IP互连是SoC设计中常遇到的问题。
Memory Design of Dedicated Architecture for Volume Rendering 一种体绘制专用体系结构存储器的设计
The interface memory control design between DWT and bit-plane encoder DWT和位平面编码器的接口存储控制设计
Shallowly Discusses the Relational Database Memory Design 浅谈关系数据库的存储设计
Data Memory Design of Vehicle-Carrying Test System in Vehicle Impact Experiments 汽车碰撞实验车载测试系统中数据存储的实现
This article to the database memory system design from the introversion on the database application system memory design, the floppy disk layout optimization and the disposition, the RAID performance and the fail-safe analysis and so on several aspects carries on the statement. 对数据库存储系统设计从内向外就数据库应用系统内存设计、磁盘布局优化和配置、RAID性能和可靠性分析等几个方面进行了研究。
This paper studies the design of IP configuration, data paths and memory design, focusing on architecture design of AAC decoder SoC based on microprocessor core. Finally, an MPEG-4 AAC decoder SoC chip based on embedded microprocessor is developed successfully. 围绕基于微处理器核的AAC解码器结构设计展开讨论,对IP定制、数据通路及存储设计进行了研究,并成功开发了一个基于微处理器核的MPEG-4AAC解码系统芯片。
A way combined based on-line configurable cache and 2-level TLB MMU micro-architecture is proposed in memory subsystem design. 内存子系统的设计中提出了基于组拼合的可在线配置Cache和两级TLB结构的全综合设计MMU。
Link layer interface module design factor is shared memory design. 链路层接口模块的设计要点是共享存储器访问的设计。
It proposes analysis focused on routing issues in high-speed memory design, and uses of DCI ( Digitally Controlled Impedance) to make signal features integrate. 最后,本文还分析了高速电路系统中可能出现的信号完整性问题,着重就高速存储器设计的布线问题进行了分析,并提出了使用DCI(DigitallyControlledImpedance)功能改善信号完整性。
The memory design is an integral part in the design of digital systems, it has been widely used in the field of electronic communications, consumer electronics, personal computers, large-scale computer, and satellite, etc.. 存储器设计是当前数字系统设计中不可或缺的组成部分,在电子通信、消费类电子产品、个人电脑、大型电脑、卫星等领域中都有存储器的广泛应用。
This thesis is based on a DSP design project in XX research institute, including two parts of work: cache controller design and cache memory design. 本文的研究工作以XX研究所的xxDSP项目为基础,分为两个部分:cache控制器设计和cache存储器的设计。
Butterfly design, address, independent dual-port memory design, the design of the complex multiplier and twiddle factor MATLAB software generation. Fourth, on the basis of the outline design, image generation module detailed design. 详细介绍了蝶形器的设计、地址产生、独立双端口存储器设计、复数乘法器的设计和旋转因子的MATLAB软件生成。第四,在概要设计的基础上,对图像生成模块进行了详细的设计。
The design of the system mainly includes the clock circuit design, peripheral memory circuit design, gigabit Ethernet interface design, image sampling input/ output interface design, and so on. 该系统的设计主要包括时钟电路设计、外围存储器电路设计、千兆以太网接口设计、图像采集输入输出接口设计等等。
System hardware design includes: control unit design, the synchronization signal unit design, memory cell design and power design. 系统硬件设计包括:控制单元的设计、同步信号发生单元的设计、存储单元的设计和电源设计。
Its retrieval subsystem realized constructing indexer, database memory design and searcher design on the basis of relative work such as document data process, information extracting. Finally, the system realized Full-text Retrieval. 其中检索部分在文档数据加工、信息筛选的基础上,完成构建索引、数据记录存储、检索器设计和索引优化,最终实现了全文检索。